Edouard BECHETOILLE
French citizen
edouard.bechetoille(¯a_)cpe.fr
2003-2004 3rd Year at CPE Lyon (French Engineering School of Chemistry, Physics and Electronics, higher education). MSc Graduated in September 2004 in fields: multiprocessor treatment processing card, DSP, network equipments and technologies.
Specialised in integrated electronics with a Master of Research equivalent Diploma associate with another Lyon University Schools. Semiconductors Physics, MOS Technology, Analog and Digital circuit design, VHDL, micro sensors.
2000-2002 1st and 2nd Year at CPE. Main subjects: General Electronics, Analog Integrated Circuit, Logic circuit, Sequential Logic, Applied Mathematics, Signal processing, Linear Systems, Imaging processing, Physics, Electrical Engineering.
Project associated with EM Lyon (Lyon Management School): part of a six-member team creating a company, learning every specification of a company.
1997-2000.1 Preparatory classes, Grenoble, FRANCE.
Three Years full-time higher education for competitive admission to one of the leading Science and Engineering Schools. Main subjects: Mathematics, Physics and Chemistry.
1997 Baccalauréate in Science (High School leaving Diploma)
Since the Research Engineer CNRS - IN2P3 - IPNL.
1st December 2006 ASIC design for physics experiments.
October 2005 Associate Engineer. INRIA Rhône-alpes, ENS Lyon, LIP UMR5668, ARENAIRE
/ November 2006 - Software development, Floating-point Library for fixed-point architecture. Necessary knowledge in DSP, compiling, algorithm, assembly. Target aware algorithms. Performances tests.
- Organising team member of JNAO06 : a French national arithmetic meet.
Mars-Sept 2005 Engineer. INRIA Rhône-alpes, ENS Lyon, France. COMPSYS project automatized partitioning for High Level Synthesis Tool. Development of MMAlpha environment under Emacs and Mathematica. MMAlpha is a parser which generates synthesisable VHDL suitable for highly pipelined applications. Implementation of memory principle in MMALPHA, in order to use the predefined RAM bloc inside FPGA's. Making FFT example for proper verification.
Mars-août 04 Analog Designer. PHILIPS Semiconductors Nijmegen, THE NETHERLANDS: optimisation of a Narrow Band FM PLL of the sound signal of a One Chip TV. Weak signal coefficients calculation, transient simulations with CADENCE, modelling, improvement of the circuit bottleneck.
2002-2003 Trainee Engineer, MESSIER-BUGATTI (SNECMA subsidiary), Villeurbanne, FRANCE. Workforce employee qualification program settlement. Inventory of needed skills. Creating and teaching courses aimed to production operators. Investigation on nodular supplying an electromagnetic-induction heating system. Data analysis, behavioural models, prophetic maintenance.
Summer 2001 Dispatch agent, SCHNEIDER ELECTRIC, Grenoble FRANCE. 4 weeks, working in a dispatch office. Responsible for phoning client, sending their order.
Summer 2000 Chemicals operator, AQUAZUR, Crolles, FRANCE. I cleaned paper mills with chemicals such as Hydrochloric, and Nitric acid.
Summer 1999 Laboratory assistant, HOUSEMAN, Manchester, UK. I worked in each department of the laboratory (quality control, microbiology, permacare, and sample analysis).
French : native
English : fluent
German : good working knowledge
Dutch : basic knowledge
Programming : C/C++ on Linux or Windows, Prolog, VHDL
Software : Microsoft Office, CADENCE, VisualDSP, MathCad, Mathlab, ModelSim
— CMOS Charge amplifier for liquid argon Time Projection Chamber detectors, WOLTE8 June 22-25 2008
— Charge Sensitive Amplifier (CSA) in cold gas of Liquid Argon (LAr) Time Projection Chamber (TPC), JINST_090P_1010 [Twepp-10]
Association member of the “Journée Entreprise” 2004. Prospecting team in order to contact companies to create a link between them and our school.
Handball-3 years CPE team, inter-university champion in 2003, Hapkido (self-defence). snowboard.