Edouard BECHETOILLE Homepage

Member of COMPSYS, Compilation and Embedded Computing Systems

INRIALPES Expert Engineer from March 2005 to September 2005

Presentation

CV [.doc | HTML]

Research axes

MMAlpha is a parser which generates VHDL suitable for highly pipelined applications.

• Use of Fixed Point arithmetic in MMALPHA
• Memory implementation in MMALPHA, in order to use the predefined RAM bloc inside FPGA's.
  Aim : handle resources constraints.

Matrix Vector multiplication exemple	Fixed Point Precision exemple

Documents